A multiport data network switch permits data communication among a plurality of media stations in a local area network. Each station in the network is associated with a port of the switch. Data frames, or packets, are transferred between stations by means of data network switch media access control (MAC) circuitry, or "engines," for each switch port. The network switch passes data frames received from a transmitting station to a destination station based on the header information in the received data frame. The switch can link the network to other networks through a router connected to one or more switch ports.
The MAC circuitry for each port must resolve contentions for traffic communication and data collisions among network stations. For example, the ISO 8802 (IEEE/ANSI 802.3) Standard specifies a carrier-sense multiple access with collision detection (CSMA/CD) interface to listen for traffic on the media. Collision detection is performed by the media devices and reported to the MAC engines. Detection of collision will cause the transmission of data to be rescheduled to a time determined by a random backoff algorithm specified by the ISO Standard. Thus, at the end of enforcing a collision, the CSMA/CD sublayer delays before attempting to re-transmit the frame. The delay is an integer multiple of slot time. The number of slot times to delay before the nth re-transmission is to be chosen as a uniformly distributed random integer. Conventional network switches typically provide a random number generator within the MAC engine at each port to generate the collision backoff interval.
As data networks become more robust, the demand grows for a greater number of switch ports and the capacity to handle the increase in network stations and density of data traffic. The resulting operational complexities impose challenges to the design of semiconductor hardware. Integration of the switch functionalities on a single multiport chip makes efficient use of chip architecture even more critical. If similar functions are executed at each of a plurality of ports, then discrete provision of similar circuitry at each port should be avoided if possible. The need exists to identify those switch port functions that can be performed by shared common integrated chip elements and to provide appropriate implementation to eliminate any unnecessary redundancies.